"Most pulser failures are not exotic. They are predictable consequences of habits the user developed working with low-voltage instruments and brought along into the high-voltage world."
Working with high-power pulsers is not the same as working with bench DMMs and signal generators. Three things change. The energies are larger, often by orders of magnitude. The rise times are faster, which means parasitic inductances and capacitances that did not matter in slow circuits suddenly drive the dynamics. And the failure modes are dramatic: instead of a flickering display, you get arcs, smoke, and damaged equipment that may or may not include the operator.
This chapter catalogs the common failures and the habits that prevent them. Most of them are obvious in retrospect. They cause expensive repairs anyway, because the obvious habits from low-voltage work are dangerously wrong at high power.
The output cable is the single most common source of pulser failures returned for service. The reasons are predictable.
Never disconnect the output cable or the load while a pulser is firing. The shock hazard to personnel is the primary concern, but the equipment also suffers. When a pulse fires into an open circuit, the pulser sees an instantaneous infinite impedance. Voltage doubles at the open end (transmission-line theory), and that doubled voltage feeds back to the switch as a reflection. Most pulsers have overvoltage protection that triggers in this case, but the protection components themselves take damage from repeated activations.
The rule is simple: disable the trigger or power down the pulser before touching any output connection. Modern BNC pulsers help here with safety interlocks: the PVX series ships with a BNC-shorted dummy connector that must be installed for the device to output, and a removed connector triggers an immediate disable.
The output impedance of a pulser is matched to a specific cable type by design. Use the cable shipped with the device. Substituting cable types because "they all look like coax" leads to overshoot, ringing, and unexpected pulse fidelity loss. Common BNC-DEI cable assignments:
The flexible 50 Ω coax in your bench drawer will physically fit the connectors on most of these. It will not work correctly. The 10 kV pulser into RG-58 is not a successful experiment.
For voltage pulsers driving capacitive loads, the cable's distributed capacitance adds to the load capacitance. Six feet of RG-59 contributes about 126 pF, and that adds directly into the C × V² × F power equation. If the data sheet quotes a maximum frequency assuming 6 ft of cable, doubling the cable length to 12 ft halves the maximum allowed frequency at the same voltage and load.
Practical rule: keep output cables as short as the geometry allows. If the load is 10 ft from the pulser, 10 ft of cable. If the load is 3 ft away, 3 ft of cable. The temptation to coil up extra length "for flexibility" costs you in heat and pulse fidelity.
When a pulse encounters an impedance discontinuity (a connector, a load that does not match the cable, an open or short), part of the pulse reflects back toward the source. The reflected wave interacts with the original pulse and produces overshoot, ringing, and ghost pulses on the scope trace.
Figure 3.1, Classic reflection signature on a mismatched cable. The overshoot at the rising edge is the first reflection arriving back at the pulser output. The damped ringing is the round-trip echo bouncing several times before energy dissipates. Termination at the load end eliminates almost all of this.
A fast scope trace with overshoot and ringing has a tell: the ring frequency reveals the round-trip time of the cable. For a 1 m cable with 0.66c propagation velocity, round trip is 10 ns. If you see ringing at 100 MHz, the period is 10 ns, and the ringing is round-trip resonance. That diagnostic almost always points at impedance mismatch.
Three options, in order of preference:
For severe-cases or unusual loads, the best practice is to model the system in SPICE before you build it. Almost every modern pulser data sheet includes a SPICE-compatible output network model, and ten minutes of simulation save days of bench debugging.
The big shift from low-voltage to high-voltage work is that wire inductance starts to matter. A foot of straight 18 AWG wire has about 300 nH of inductance. At 1 MHz, that is 1.9 Ω of impedance: barely noticeable. At 100 MHz (a 3.5 ns rise time pulser), it is 190 Ω, more than enough to drop kilovolts at high current and to ring with stray capacitances.
The places where parasitic inductance causes problems:
The path from the gate driver output to the MOSFET gate, and back through the source, forms a loop. The loop area times the rate of change of current sets the inductive voltage drop. A noisy gate drive loop causes the MOSFET to false-trigger (Miller turn-on, see 3.5) or to miss commanded transitions. The fix is geometric: keep the gate-to-source loop as small as physically possible. On a PCB, this means routing gate and source returns directly adjacent, often as a coplanar stripe. In a multi-MOSFET stack, every stage gets its own short loop, fed from a transformer or a fast buffer.
If the pulser output current returns through a path that is not directly adjacent to the outgoing conductor, the output loop area is large. Stray inductance in that loop limits dI/dt and adds ringing. The fix is to use coaxial cable (which forces the return current to flow as a sheath around the center conductor), and to ensure the load is a coaxial structure too. Substituting a single wire for the coax shield is a common mistake on the bench. It works at low frequencies. It fails badly at fast rise times.
The equivalent series inductance (ESL) of the storage capacitor bank limits how fast the pulser can extract energy. A 100 µF electrolytic with 50 nH ESL cannot deliver a 100 ns rise pulse, period. The capacitor itself is the limit. For fast-rise applications, use ceramic or film capacitors with low ESL, paralleled in low-inductance bus structures (the rail-bus design from Chapter 1's Manhattan Project lineage).
This one is its own category because it bites every solid-state pulser engineer at least once. Here is the mechanism.
A power MOSFET has a parasitic capacitance from drain to gate, called Cgd or "Miller capacitance." Typical values are 50 to 500 pF for a few-kV-class MOSFET. When the drain voltage swings rapidly (high dV/dt during a switching transition), the Miller capacitance couples that dV/dt into the gate as a current:
i_miller = C_gd × dV/dt
That current flows through whatever impedance is between the gate and ground. If the gate driver is fast and low-impedance (a 10 Ω driver, say), the gate voltage barely moves. If the gate driver is slow or high-impedance (or if the source has stray inductance in series), the gate voltage rises, the MOSFET partially turns on, the dV/dt slows down, and you have an unstable feedback loop.
Symptoms are subtle: pulses look right at low repetition rate, then degrade as PRF climbs. Switching losses go up, the device heats, and eventually a thermal failure ends the experiment. On a scope, the gate-source voltage shows a small bump at the time of the drain transition.
Fixes, in order of practicality:
When a high dV/dt signal travels through a cable to a load, the cable's parasitic capacitance to its surroundings acts as a current path back to the pulser. That current flows on the outside of the cable shield, through whatever stray capacitance exists between the cable, the load fixture, and earth ground. It is called a common-mode current because it flows in the same direction on both the center conductor and the shield (rather than the equal-and-opposite differential-mode current of normal signal flow).
Common-mode currents cause two problems. First, they couple into nearby instruments (oscilloscopes, controllers, computers) and cause apparent "noise" that scales with pulser dV/dt. Second, they create ground bounce: the ground reference at the load is no longer at the same voltage as the ground reference at the pulser, because there is real impedance between them carrying real current. Ground bounce shows up as common-mode error on differential measurements, as triggering errors on logic circuits sharing the same ground, and as a generic "ground noise" that scales with PRF.
The fix is twofold. First, minimize common-mode current by keeping the cable short and away from grounded surfaces. Second, block whatever common-mode current does flow with a common-mode choke (a ferrite ring around the cable) or with optical isolation between the high-voltage circuit and any low-voltage systems.
For oscilloscope measurements specifically: float the scope properly with a differential probe or an isolation amplifier, never by lifting the safety ground (which is dangerous and sometimes illegal). Chapter 7 develops this in full.
In voltage pulsers, anywhere two conductors are close enough that the field between them exceeds the breakdown strength of the intervening dielectric, a small ionization event happens. If the dielectric is air, the breakdown field is roughly 30 kV/cm at sea level. For 1 cm spacing, that means breakdown at 30 kV. For 1 mm spacing, breakdown at 3 kV. For 0.1 mm, breakdown at 300 V. Most modern PCBs have spacings well below 1 mm in places, and at kilovolt levels you can get partial discharge on a board that looks fine to the eye.
Partial discharge is not a full arc. It is a localized ionization that does not propagate to a complete short, but that does carbonize the dielectric over time and eventually leads to full breakdown. On a PCB, partial discharge along surface traces leaves a black tracking pattern that you can see under a microscope. In an encapsulated device, you cannot see it but the device fails after some hours of operation, suddenly.
The remedies are geometric:
Voltages above 30 kV in air are difficult and require specialized engineering. Above 100 kV, oil immersion or SF6 is the standard answer in industrial systems, and water is the standard in pulsed-power physics applications because of its high dielectric strength under nanosecond stresses.
The term "floating" appears constantly in pulsed-power discussions, and it means different things in different contexts. Three usages:
The dangerous kind is the third. Floating a scope means the chassis and all the connected probe grounds are at whatever voltage the load develops. A 10 kV pulser into a load you are probing with a "floated" scope means the scope chassis is at 10 kV. Touching the scope while it is firing will electrocute you. There is no scenario where this is the right thing to do.
When a pulser comes back from the field showing strange behavior, work through this checklist before opening the case.
If all seven check out clean and the pulser is still misbehaving, it is time to open the case. Do that with the unit unplugged, capacitor bank discharged through a bleeder resistor, and a partner present. High-voltage capacitor banks hold dangerous charges for hours after the supply is disconnected. Treat them with respect.
A pulser drives an open-circuit cable. What happens to the voltage at the open end during the pulse? a. The voltage stays the same as the source. b. The voltage drops to zero. c. The voltage doubles due to reflection. d. The voltage oscillates randomly.
Miller turn-on is caused by: a. Bias on the source resistor. b. dV/dt at the drain coupling current through Cgd into the gate. c. Thermal runaway in the channel. d. Common-mode current on the trigger cable.
A 10 ns ring period on a scope trace from a pulser-cable system most likely indicates: a. EMI pickup from a nearby AC line. b. Round-trip resonance on a 1 m cable with mismatched impedance. c. Switch ringing from gate-loop inductance. d. Power supply ripple.
A user replaces the supplied RG-62 cable on a PVX-4150 with a 50 Ω BNC cable that fits the connector. The result is most likely: a. No effect because the impedance difference is small. b. Overshoot and ringing on the pulse waveform. c. The pulser stops working entirely. d. Reduced power dissipation in the pulser.
Which of the following is NOT a safe way to make a measurement on a floating load? a. Use a differential probe with adequate voltage rating. b. Use a fiber-coupled isolation amplifier. c. Lift the oscilloscope's safety ground. d. Use a current-viewing resistor with a galvanically isolated digitizer.
Partial discharge typically leaves what visible evidence? a. A clean burn mark across all conductors. b. Carbonized tracking patterns along the dielectric surface. c. Melted solder joints. d. Discolored heatsinks.
The single most common cause of pulser returns from the field is: a. Switch failure in the output stage. b. Software firmware bugs. c. Cable and connector problems, including wrong cable substitution and disconnect-under-load events. d. Power supply failure.
The same seven questions, graded instantly with your score saved on this device.
Answer key at end of book.
IPC-2221. Generic standard on printed board design, including the voltage-versus-spacing tables that govern partial-discharge clearance. Essential for anyone laying out a high-voltage PCB.
Williams, T. EMC for Product Designers. Newnes, multiple editions. The clearest practical treatment of common-mode currents and how they cause "noise" that has nothing to do with EMI.
Mohan, N., Undeland, T.M., and Robbins, W.P. Power Electronics: Converters, Applications, and Design. Wiley. Chapter 22 on gate-drive design covers Miller turn-on and the geometric remedies in detail.
Application notes from gate-driver manufacturers (Analog Devices, Texas Instruments, Infineon) on Miller-effect mitigation. Look for "high-side gate driver" application notes specifically.
NFPA 70E. Standard for electrical safety in the workplace. Required reading for anyone who works on energized high-voltage equipment.
End of Chapter 3.
Chapter 4 (Safety) follows.